Pixel modulation apparatus and method thereof

ABSTRACT

A pixel modulation apparatus for converting pixel data D composed of N1 bits to a pixel data signal composed of one bit. The pixel data D is input into the apparatus at a pixel period TO. The apparatus includes a first data conversion unit which converts the pixel data D to pixel data D1 expanded to N2 bits (N2&gt;N1) at the period T0, a second data conversion unit which converts the pixel data D 1  to pixel data D 2  composed of N3/m bits at a period T0/m, a third data conversion unit which inputs n data from among the pixel data D 2  and pixel data Dd 2  constituting the pixel data D 2  before having the period T0/m to execute logical sum operations a predetermined number (equal to or less than n) of times to convert the n data to pixel data D 3  composed of N3 bits, including additional data corresponding to the predetermined number, and a fourth data conversion unit which converts the pixel data D 3  to the pixel data signal composed of one bit at the period T0/m.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a pixel modulation apparatus anda method thereof, and more particularly to a pixel modulation apparatuscapable of performing high-accuracy pulse width modulation forcontrolling the light emission of a laser on a pixel basis in an imageforming apparatus which uses the laser to form an image, and a method ofsuch pixel modulation.

[0003] 2. Related Background Art

[0004] An image forming apparatus using a laser beam has been used asone of apparatus performing the control of the quantity of a laser beamby means of a pulse width modulation. As for such an image formingapparatus, first, a color image forming apparatus is simply described asan example thereof.

[0005] A color image forming process of such an color image formingapparatus generally uses four kinds of toners of yellow (Y), cyan (C),magenta (Mg) and black (Bk) severally. Such a color image formingprocess takes a time four times as long as the time necessary for animage forming process of a conventional image forming apparatus forminga monochrome image if no measures for shortening the time are taken.Because of this, an image forming process adopts use of fourphotosensitive drums for the respective four colors and use of atwo-beam laser capable of writing two lines at the same time.

[0006]FIG. 1 is a schematic diagram of a conventional four-drum typeimage forming apparatus. In the apparatus, photosensitive drums 18 a, 18b, 18 c and 18 d are disposed in a line. A different color is allottedto each of the photosensitive drums 18 a-18 d. The toner of each coloris sequentially transferred to a photographic printing paper 26, and acolor image is reproduced on the photographic printing paper 26. Each ofthe photosensitive drums 18 a-18 d is provided with an image writingportion shown in FIG. 2. The image writing portion forms anelectrostatic latent image on the photosensitive drum by means of alaser beam. The operations of the image writing portion shown in FIG. 2are described in the following.

DESCRIPTIONS OF IMAGE WRITING PORTION

[0007] A laser chip 21 is one of a two-beam type having laser diodes aand b. The laser chip 21 also has a photodiode c receiving the backlight from each of the laser diodes a and b.

[0008] Driving currents Id1 and Id2 for controlling the emission oflight of each of the laser diodes b and a, respectively, are supplied tothe laser diodes a and b from a laser diode (LD) driver 22. Thephotodiode c outputs monitor current Im according to the quantity of theback light. The monitor current Im is input into the LD driver 22. TheLD driver 22 performs the auto-power control (APC) of the quantities ofthe light emitted by the laser diodes a and b on the basis of themonitor current Im. The interval between the laser emission points ofthe laser chip 21 cannot be equal to the interval between pixels (about42 μm in case of 600 dots per inch (dpi)) owing to the limitation on themanufacture of the laser chip 21. Because of this problem, as shown inFIG. 3, the laser diodes a and b are obliquely disposed such that twobeams A and B are spotted at positions distant from each other by, forexample, 16 pixels in the laser scanning direction in pixel regionsenclosed by grid lines.

[0009] Laser beams emitted by the laser chip 21 are deflected by apolygon mirror 16 fixed on a motor shaft to rotate in the directionshown by an arrow in FIG. 2. Thereby, the deflected laser beams scan ona photosensitive drum 18. A f-θ lens 17 is for collecting the deflectedlaser beams on the photosensitive drum 18 such that their linearvelocities are constant. If the photosensitive drum 18 and the toner forprinting are previously charged electrostatically by the predeterminedquantities of electrostatic charges, the quantity of the toner forprinting adhering to the photosensitive drum 18 changes according to thequantity of the light irradiating the photosensitive drum 18.Consequently, it becomes possible to print an image having intermediategradations. A BD mirror 19 is disposed at a position in a mechanicallyfixed positional relation to the photosensitive drum 18. Laser beamsreflected by the BD mirror 19 are input into a light receiving diode 20.The received laser beams are used for the detection of the positions onthe photosensitive drum 18, from which information is written. An outputof the light receiving diode 20 is input into a horizontal synchronizingsignal generating circuit 24, and the horizontal synchronizing signalgenerating circuit 24 generates a horizontal synchronizing signal BD.

[0010] The horizontal synchronizing signal BD is input into a pixelmodulation circuit 23. The pixel modulation circuit 23 generates a pixelclock synchronized with the horizontal synchronizing signal BD or apixel clock having a frequency which is a coefficient multiple of thefrequency of the horizontal synchronizing signal. Read clocks RK1 andRK2 for the reading of pixel data are input into a pixel data generatingunit 25 on the basis of the pixel clock.

[0011] The pixel data generating unit 25 outputs pixel data D1 and D2and respective write clocks WK1 and WK2 to the pixel modulation circuit23. The pixel data generating unit 25 generates the pixel data D1 and D2by reading an original with a scanner or the like. The pixel modulationcircuit 23 outputs pixel modulation signals ON1 and ON2 for making itpossible to modulate the quantity of laser light desirably, to the LDdriver 22 on the basis of the pixel data D1 and D2. The pixel modulationsignals ON1 and ON2 are pulse width modulation signals for controllingthe quantity of laser light on the basis of the periods of laserirradiation time. FIG. 4A shows an example of a pixel modulation signaltaking different pulse widths P1, P2, P3 and P4. If a laser diode isturned on in accordance with these pulse widths P1-P4, the desiredcontrol of quantity of light to the photosensitive drum 18 can berealized. There are two major methods of pixel modulation, which areapplicable to the pixel modulation circuit 23.

[0012] Digital Pixel Modulation

[0013] A pixel modulation circuit for the use of a character imageadopts the serial modulation of, for example, four bits to process apixel (composed of e.g. 600 dpi) by dividing the pixel into four pixels(composed of 2400 dpi). Dithering and the error diffusion method areused jointly to improve reproducibility of the gradation of a videoimage.

[0014] Analog Image Modulation

[0015] It is general that a pixel modulation circuit needed to reproducea further higher image quality is provided with a triangular wave signalgeneration circuit for generating an analog pixel data signal byconverting input pixel data D1 and D2 by digital-analogue (D/A)conversion to generate a triangular wave signal having a predeterminedpixel period, and a pulse width modulation circuit for generating apulse width modulation signal by comparing the signal level of thetriangular wave signal and the signal level of the aforementioned analogpixel data signal.

[0016] However, the digital pixel modulation and the analog pixelmodulation, which are used in the conventional image forming apparatus,have the following problems.

[0017] Problem 1.

[0018] Input images generally have characters and video images that aremixed together. For such input images, the conventional digital pixelmodulation could not secure sufficient number of pixel divisions, andthereby, a predetermined video image quality could not be secured.

[0019] Problem 2.

[0020] In the conventional analog pixel modulation, because a stablefast triangular wave signal generation circuit cannot be realized by thecomplementary metal-oxide semiconductor (CMOS) large scale integratedcircuit (LSI) technique, the stable fast triangular wave signalgeneration circuit has been realized by the bipolar LSI technique.Consequently, a pixel modulation circuit for video has been expensive.

[0021] Problem 3.

[0022]FIG. 4A shows an example of a pixel modulation signal includingdifferent pulse widths P1-P4. If the laser diodes a and b are lightenedin accordance with the pulse widths, a desired control of the quantityof light on the photosensitive drum 18 can be realized. However, laserdiodes do not emit light immediately after the supply of a drivingcurrent Id to them, but emit light after the passing of a delay time Tdin principle. On the other hand, when the driving current Id is cut off,the laser diodes stops their light emission in a short time.Consequently, as shown in FIG. 4B, the periods of light emission of thelaser diodes become shorter than the periods of being on of the pixelmodulation signal by the delay time Td of light emission. The laserdiodes do not emit light during the period of the pulse width P2.Consequently, the desired control of the light emission of laser diodescould not performed in the conventional digital image modulation, andthereby the quality of printing has been deteriorated.

SUMMARY OF THE INVENTION

[0023] In view of the back ground mentioned above, an object of thepresent invention is to provide a pixel modulation apparatus that caneasily generate a laser control signal suitable for various images suchas gradated images and character images and can accurately change thequantity of laser light and further can be constructed by, for example,a pure CMOS process and still further is low in cost, and a methodthereof.

[0024] Accordingly, according to a preferable embodiment of theinvention, a pixel modulation apparatus for converting pixel data Dcomposed of N1 bits input at a pixel period T0, to a pixel data signalcomposed of one bit comprising: a first data conversion unit whichconverts the pixel data D to pixel data D1 expanded to N2 bits (N2>N1)at the period T0; a second data conversion unit which converts the pixeldata D1 to pixel data D2 composed of N3/m bits at a period T0/m; a thirddata conversion unit which inputs n data from among the pixel data D2and pixel data Dd2 constituting the pixel data D2 preceding by theperiod T0/m to execute logical sum operations a predetermined number(equal to or less than n) of times to convert the input n data to pixeldata D3 composed of N3 bits including additional data corresponding tothe predetermined number; and a fourth data conversion unit whichconverts the pixel data D3 to the pixel data signal composed of one bitat the period T0/m.

[0025] Moreover, a pixel modulation method according to an anotherpreferable embodiment of the invention, of converting pixel data Dcomposed of N1 bits input at a pixel period T0, to a pixel data signalcomposed of one bit, comprising: a first data conversion step ofconverting the pixel data D to pixel data D1 expanded to N2 bits (N2>N1)at the period T0; a second data conversion step of converting the pixeldata D1 to pixel data D2 composed of N3/m bits at a period T0/m; a thirddata conversion step of inputting n data from among the pixel data D2and pixel data Dd2 constituting the pixel data D2 preceding by theperiod T0/m to execute logical sum operations a predetermined number(equal to or less than n) of times to convert the input n data to pixeldata D3 composed of N3 bits, including additional data corresponding tothe predetermined number; and a fourth data conversion step ofconverting the pixel data D3 to the pixel data signal composed of onebit at the period T0/m.

[0026] Other objects, features and advantages of he invention willbecome apparent from the following detailed description taken inconjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0027]FIG. 1 is a schematic diagram of a conventional four-drum typeimage forming apparatus;

[0028]FIG. 2 is a block diagram showing the configuration of the imagewriting portion of the image forming apparatus;

[0029]FIG. 3 is a diagram for illustrating the disposition relationbetween two laser diodes;

[0030]FIG. 4A and FIG. 4B are timing charts for illustrating theoperation of a conventional pixel modulation circuit;

[0031]FIG. 5 is a block diagram of a pixel modulation circuit accordingto the present invention;

[0032]FIG. 6 is a block diagram of the data conversion circuit 2 shownin FIG. 5;

[0033]FIG. 7 is a block diagram of a high precision four-bit serialconversion circuit to be used in the data conversion circuits 2 and 4;

[0034]FIGS. 8A, 8B, 8C, 8D, 8E, 8F, 8G, 8H and 8I are timing charts forillustrating the operation of the data conversion circuit 2;

[0035]FIGS. 9A, 9B, 9C and 9D are timing charts for illustrating theoperation of the pixel modulation apparatus according to the presentinvention;

[0036]FIG. 10 is a block diagram of the data conversion circuit 3 shownin FIG. 5;

[0037]FIG. 11 is a diagram showing a data adding circuit to be used inthe data conversion circuit 3;

[0038]FIG. 12 is a truth table of a decoder circuit to be used in thedata conversion circuit 3;

[0039]FIG. 13 is a diagram showing the decoder circuit to be used in thedata conversion circuit 3;

[0040]FIG. 14 is a diagram showing a DLL circuit to be used in the pixelmodulation apparatus;

[0041]FIG. 15 is a diagram showing a controlled delay circuit to be usedin the DLL circuit shown in FIG. 14;

[0042]FIGS. 16A, 16B, 16C, 16D, 16E, 16F, 16G, 16H, 16I, 16J, 16K, 16L,16M, 16N and 16O are timing charts for illustrating the operation of thedata conversion circuit 4;

[0043]FIG. 17 is a block diagram of the data conversion circuit 4 shownin FIG. 5;

[0044]FIGS. 18A, 18B and 18C are timing charts showing the operation ofthe pixel modulation circuit according to the present invention; and

[0045]FIG. 19 is a diagram showing a high precision twofold multipliedclock generating circuit to be used in the data conversion circuit 4.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0046]FIG. 5 shows a pixel modulation circuit according to the presentinvention applied to a color printer using four color pieces of toner ofyellow (Y), cyan (Cy), magenta (Mg) and black (Bk). The pixel modulationcircuit is composed of four data conversion circuits 1-4. The pixelmodulation circuit is provided for each laser beam. The otherconfiguration of the image writing portion provided with the pixelmodulation circuit is the same as that shown in FIG. 2.

[0047] Description of Data Conversion Circuit 1

[0048] Each of pixel data D (composed of six bits in this case)generated by picking up an object image with a scanner or the like and awrite clock WK are input into a 6-to-32-bit data conversion circuit 1for converting 6 bit data to 32 bit data. Then, the pixel data D areconverted to 32 bit data D1.

[0049] The 6-to-32-bit data conversion circuit 1 is, for example, a64-word random access memory (RAM). One word is composed of 32 bits. Thepixel data D are input to the address lines of the RAM, and the pixeldata D1 are output from the word lines of the RAM as data D131 to D100synchronized with read clocks CK1 and CK2. The pixel data D ispreviously written into each of desired word data in the RAM by use ofserial transfer lines including serial transferring clocks KS,transferring serial data DS and transferring data load signals LS. It isneedless to say that the data conversion circuit 1 may be a read onlymemory (ROM) in which the contents have previously been written fixedly.

[0050] Description of Data Conversion Circuit 2

[0051] The pixel data D1 are input into a 32-to-8-bit data conversioncircuit 2. The input pixel data D1 is serially converted to 8-bit imagedata D2 by means of input clocks K1.

[0052] As shown in FIG. 6, the data conversion circuit 2 is composed ofeight 4-bit serial conversion circuits 11 a, 11 b, 11 c, 11 d, 11 e, 11f, 11 g and 11 h. It is desirable to use the 4-bit serial conversioncircuit that is shown in FIG. 7 and is composed of only inverters andtwo-input inverters, both being suitable for high speed operation.

[0053] As clock inputs k0, k1, k2 and k3, four-phase clocks K10, K11,K12 and K13, which are respectively shown in FIGS. 8D to 8G and areobtained by the dividing of a clock signal having the period of T0/4 (T0indicates a pixel period) shown in FIG. 8A into a frequency of onefourth of the frequency of the clock signal shown in FIG. 8A, arerespectively input. The clock signal having the period of T0/4 caneasily be generated by means of a phase-locked loop (PLL) circuit.

[0054] Data d3 are output to a serial data output ps4 terminal in aregion z1 shown in FIGS. 8A-8I by the clock inputs k0 and k1. Data d2are output to a serial data output ps4 terminal in a region z2 by theclock inputs k1 and k2. Data d1 are output to a serial data output ps4terminal in a region z3 by the clock inputs k2 and k3. Data d0 areoutput to a serial data output ps4 terminal in a region z4 by the clockinputs k3 and k0. Thereby the four-bit seal conversions of input data d3to d0 are realized.

[0055] As shown in FIG. 6, as the input data d3 to d0 of the serialconversion circuits 11 a-11 h, the following data are respectivelyinput. As for the uppermost bit pixel data D27, data D131, D123, D115and D107 are input. As for pixel data D26, data D130, D122, D114 andD106 are input. As for pixel data D25, data D129, D121, D113 and D105are input. As for pixel data D24, data D128, D120, D112 and D104 areinput. As for pixel data D23, data D127, D119, D111 and D103 are input.As for pixel data D22, data D126, D118, D110 and D102 are input. As forpixel data D21, data D125, D117, D109 and D101 are input. As for pixeldata D20, data D124, D116, D108 and D100 are input.

[0056] Incidentally, for the ensuring of the operation of dataconversion circuit 2, it is desirable to generate the high order inputdata D131-D116 of pixel data D1 as shown in FIG. 8H by means of theclock CK1 shown in FIG. 8B, and to generate the low order input dataD115 to D100 of the pixel data D1 as shown in FIG. 8I by means of theclock CK2 shown in FIG. 8C. Thereby, the operation of the dataconversion circuit 2 is stabilized.

[0057]FIGS. 9A to 9D are referred to while the data conversion operationmentioned above is described. The input 6-bit pixel data D having theperiod T0 shown in FIG. 9A are expanded to the 32-bit pixel data D1having the period TO shown in FIG. 9B. The 32-bit pixel data D1 are thenconverted to the 8-bit pixel data D2 having the period T0/4 as shown inFIG. 9C.

[0058] Description of Data Conversion Circuit 3

[0059] The pixel data D27 to D20 are input into the data conversioncircuit 3. The configuration of the data conversion circuit 3 is shownin FIG. 10. In FIG. 10, the pixel data D27 to D20 are latched by latchcircuits 8 a and 8 b by use of a clock CK3 having the period T0/4 and apredetermined phase to generate pixel data Da7, Da6, Da5, Da4, Da3, Da2,Da1 and Da0, and Db6, Db5, Db4, Db3, Db2, Db1 and Db0 delayed from thepixel data Da7 to Da0, respectively. The pixel data Da7 to Da0 and Db6to Db0 are input into eight data adding circuit 10 a, 10 b, 10 c, 10 d,10 e, 10 f, 10 g and 10 h having the same structure severally. The dataadding circuits 10 a to 10 h respectively output converted pixel dataD37, D36, D35, D34, D33, D32, D31 and D30. Moreover, control signals s1,s2, s3, s4, s5, s6 and s7 are input to each of the data adding circuit10 a to 10 h. The control signals s1 to s7 are generated by a decoder 9to which pulse width adding data L2, L1 and L0 are input.

[0060] The data adding circuits 10 a to 10 h are severally configured asan OR circuit of eight data Din, Dx1, Dx2, Dx3, Dx4, Dx5, Dx6 and Dx7,as shown in FIG. 11. Incidentally, because the other input terminal of atwo-input NAND circuit to which the data Din is input is connected witha power supply C, the data Din is always output. The OR operation of thedata Din with the other data Dx1 to Dx7 is executed when the controlsignals s1 to s7 take an H level, respectively. Then, data Dout isoutput.

[0061] In the data adding circuit 10 h, the pixel data Da0, Da1, Da2,Da3, Da4, Da5, Da6 and Da7 are input as the data Din, Dx1, Dx2, Dx3,Dx4, Dx5, Dx6 and Dx7, respectively, and the converted pixel data D30 isoutput.

[0062] In the data adding circuit 10 g the pixel data Da1, Da2, Da3,Da4, Da5, Da6, Da7 and Db0 are input as the data Din, Dx1, Dx2, Dx3,Dx4, Dx5, Dx6 and Dx7, respectively, and the converted pixel data D31 isoutput.

[0063] In the data adding circuit 10 f, the pixel data Da2, Da3, Da4,Da5, Da6, Da7, Db0 and Db1 are input as the data Din, Dx1, Dx2, Dx3,Dx4, Dx5, Dx6 and Dx7, respectively, and the converted pixel data D32 isoutput.

[0064] In the data adding circuit 10 e, the pixel data Da3, Da4, Da5,Da6, Da7, Dab0, Db1 and Db2 are input as the data Din, Dx1, Dx2, Dx3,Dx4, Dx5, Dx6 and Dx7, respectively, and the converted pixel data D33 isoutput.

[0065] In the data adding circuit 10 d, the pixel data Da4, Da5, Da6,Da7, Db0, Db1, D62 and Db3 are input as the data Din, Dx1, Dx2, Dx3,Dx4, Dx5, Dx6 and Dx7, respectively, and the converted pixel data D34 isoutput.

[0066] In the data adding circuit 10 c, the pixel data Da5, Da6, Da7,Db0, Db1, Db2, Db3 and Db4 are input as the data Din, Dx1, Dx2, Dx3,Dx4, Dx5, Dx6 and Dx7, respectively, and the converted pixel data D35 isoutput.

[0067] In the data adding circuit lob, the pixel data Da6, Da7, Db0,Db1, Db2, Db3, Db4 and Db5 are input as the data Din, Dx1, Dx2, Dx3,Dx4, Dx5, Dx6 and Dx7, respectively, and the converted pixel data D36 isoutput.

[0068] In the data adding circuit 10 a, the pixel data Da7, Db0, Db1,Db2, Db3, Db4, Db5 and Db6 are input as the data Din, Dx1, Dx2, Dx3,Dx4, Dx5, Dx6 and Dx7, respectively, and the converted pixel data D37 isoutput.

[0069]FIG. 12 shows an example of a logical truth table for thegeneration of the control signals s1 to s7 on the basis of the pulsewidth adding data L2 to L0. On such a truth table, the data addingcircuits 10 a to 10 h add the data Dx1 to Dx7 logically as the value ofthe pulse width adding data L increases. When the value of the pulsewidth adding data L is zero, the data conversion circuit 3 outputs thepixel data D2 as they are as pixel data D3. The following is eachlogical expression of the control signals s1 to s7.

S1=L2+L1+L0

S2=L2+L1

S3=L2+({double overscore (L1)}{overscore (+)}{double overscore (L0)})

S4=L2

S5=L2×({double overscore (L1)}{overscore (×)}{double overscore (L0)})

S6=L2×L1

S7=L2×L1×L0

[0070]FIG. 13 shows a circuit configuration of the decoder 9 of eachlogical expression.

[0071] Description of Data Conversion Circuit 4

[0072] The 8-bit pixel data D3 is input into the data conversion circuit4, which converts data from eight bits to four bits. The 8-bit pixeldata D3 is converted into 1-bit laser control signal ON by mean of aclock CK4 and a multi-phase clock k2, and the laser control signal ON isoutput from the data conversion circuit 4. The multi-phase clock k2 isgenerated by a DLL circuit shown in FIG. 14. A clock K having a periodT0/4 is input into a delay circuit 12 a. Delay circuits 12 a, 12 b, 12c, 12 d, 12 e, 12 f, 12 g, 12 h and 12 i all have the same structure,and each is a variable delay circuit having a delay time changeable by acontrol signal Vd. The delay circuits 12 a-12 i can severally beconfigured by, for example, a CMOS circuit shown in FIG. 15. Because theCMOS circuit shown in FIG. 15 is composed of differential circuits, theCMOS circuit can stably realize its high speed operation.

[0073] The output signals of the delay circuits 12 a and 12 i are inputinto a phase comparison circuit 13, and the phase comparison circuit 13outputs an up-pulse U and a down-pulse D. The up-pulse U and thedown-pulse D are input into a charge pump circuit 14. The charge pumpcircuit 14 generates an error signal on the basis of the up-pulse U andthe down-pulse D. The error signal is input into a control signalgeneration circuit 15. The control signal generation circuit 15 convertsthe input error signal to the control signal Vd. The control signal Vdoutput from the control signal generation circuit 15 is input into eachof the delay circuits 12 a to 12 i. The DLL circuit shown in FIG. 14 iscontrolled by the control signal Vd such that the phases of the outputsignals of the delay circuit 12 a and 12 i agree with each other.Consequently, output clocks K20, K21, K22, K23, K24, K25, K26 and K27 ofthe respective delay circuits 12 a, 12 b, 12 c, 12 d, 12 e, 12 f, 12 gand 12 h are the multi-phase clocks the phases of which are shifted fromeach other by T0/32 as shown in FIGS. 16A, 16B, 16C, 16D, 16E, 16F, 16Gand 16H respectively. The clock K20 is also used as the clock CK3 of theaforementioned data conversion circuit 3.

[0074] The configuration of the data conversion circuit 4 is shown inFIG. 17. Because the pixel data D3 are latched by the clock CK3 (orclock K20), the pixel data D3 is input into the data conversion circuit4 at a timing shown in FIG. 16I. The lower four bits D33 to D30 of thepixel data D3 are latched by a latch circuit 7. If the output clock K24is used as the clock CK4, data Dc3, Dc2, Dc1 and Dc0 of the latchcircuit 7 are output as shown in FIG. 16J. The higher four bit D37 toD34 of the pixel data D3, the data Dc3 to Dc0 and clocks K20 to K27 areinput into two serial conversion circuits 5 a and 5 b and twofoldmultiplied clock generating circuit 6.

[0075] It is preferable to configure the serial conversion circuits 5 aand 5 b in the configuration of FIG. 7, which is suitable for high speedoperation. The clocks K24, K26, K26, K20, K20, K22, K22 and K24 areinput into the serial conversion circuits 5 a and 5 b as the respectiveclock inputs k0, k1, k2, k3, k4, k5, k6 and k7 thereof. Moreover, thedata D37, D34, Dc3 and Dc0 are input into the serial conversion circuit5 a as the data d3, d2, d1 and d0 thereof. The data D36, D35, Dc2 andDc1 are input into the serial conversion circuit 5 b as the data d3, d2,d1 and d0 thereof. Consequently, as shown in FIGS. 16K and 16L, outputsignals DS1 and DS2 of the serial conversion circuit 5 a and 5 b arerespectively output as the following serially converted data. That is,the pixel data D37 and D36 are output in a region (z1+z2). The pixeldata D34 and D35 are output in a region (z3+z4). The pixel data D33 andD32 are output in a region (z5+z6). The pixel data D30 and D31 areoutput in a region (z7+z8).

[0076] It is preferable that the configuration of the twofold multipliedclock generating circuit 6 is a configuration shown in FIG. 19 in thecase where the serial conversion circuits 5 a and 5 b are configured asthe configuration of FIG. 7. The clocks K25, K27, K21, K23, K27, K21,K23 and K25 are input into the twofold multiplied clock generatingcircuit 6 as the clock inputs k0, k1, k2, k3, k4, k5, k6 and k7 thereof,respectively. In this case, a twofold multiplied clock x2k1 is output asa signal shown in FIG. 16M. That is, the twofold multiplied clock x2k1takes an L level in a region (z2+z3) and a region (z6+z7), and takes anH level in a region (z4+z5) and a region (z1+z8), as shown in FIG. 16M.On the other hand, a twofold multiplied clock x2k2 is output as a signalshown in FIG. 16N. That is, the twofold multiplied clock x2k2 takes theL level in the region (z1+z8) and the region (z4+z5), and takes the Hlevel in the region (z2+z3) and the region (z6+z7), as shown in FIG.16N. The output signals DS1 and DS2 and the twofold multiplied clocksx2k1 and x2k2 are input into a selection circuit composed of threetwo-input NAND circuit. The selection circuit outputs the laser controlsignal ON in the regions z1, z2, z3, z4, z5, z6, z7 and z8, which isshown in FIG. 160 and is serially converted from the pixel data D3 toD30.

[0077] The pixel modulation circuit, which is shown in FIG. 5 and isdescribed above, can serially convert the laser control signal ON in thepixel period TO by dividing the 32-bit pixel data D1, which have beenexpanded arbitrarily from the input pixel data D, into 32 parts, whichis more fine in comparison with the related art, as shown in FIG. 9D.Consequently, the image processing, which is a pixel modulationtechnique to be used in the reproduction of a video (or gradation) imageand is composed of techniques such as center pulse width modulation(PWM), left growing PWM, right growing PWM, contour processing in thereproduction of a highly fine character, and the like, can all berealized easily by the advance registration of data for the execution ofthe image processing in a memory in the data conversion circuit Forexample, a 64-word memory (or a RAM) (one word is composed of 32 bits)using the input pixel data D (composed of six bits) as address inputs isprepared as the memory in the data conversions circuit 1 for theachievement of the aforementioned image processing. Desired dataconversion pattern data (composed of 32 bits) corresponding to the inputpixel data D (or the address data) is previously written in this RAM.

[0078] As a method of the registration, a serial transferring method ispreferable. For the serial transfer, three signal lines for the serialtransferring clocks KS, the transferring serial data DS and thetransferring data load signals LS are generally used. The transferringserial data DS includes an address signal corresponding to the inputpixel data D, desired data conversion pattern data (composed of 32 bits)and a signal for switching over the RAM to its write mode, and thetransferring serial data DS transfers the signals and the data to theRAM. When the data conversion circuit 1 receives the load signals LS,the data conversion circuit 1 begins to write the transferring serialdata DS into the RAM. When the writing has finished, the RAM is switchedover to its read mode. Moreover, the pulse width of the laser controlsignal ON can be increased T0/32 by Tp/32 from a pulse width Tw definedby the pixel data D1 to a pulse width (Tw+7T0/32) as the value of thepulse width adding data L increases, which is input into the dataconversion circuit 3, from zero to seven. Moreover, the operation is notlimited by the output form of the laser control signal ON. Consequently,pulses, which are shown in FIG. 18B, of the laser control signal ON canbe generated with the addition of a predetermined pulse width to each ofthe pulses P1, P2, P3 and P4 of the conventional laser control signal ON(a state where the pulse width adding data L is 0 h) shown in FIG. 18Aon the basis of the pulse width adding data L. Thereby, the lightemission delay phenomenon being a fundamental characteristic of a laserdiode can be cancelled equivalently. Thus, the laser emission signalthat has been subjected to a desired control can easily be obtained asshown in FIG. 18C. All of the components of the pixel modulationcircuits can be realized by a pure CMOS semiconductor process, which canhighly integrates semiconductor elements.

[0079] Incidentally, although the descriptions concerning theaforementioned embodiment are made on the assumption that the laser beamis used as a beam for forming an image, any beam may be applied to thepresent invention as long as the beam can form an image.

[0080] According to the present embodiment, the input pixel data D canbe expanded finely based on the pixel period, and consequently the lasercontrol signal ON suitable for various images such as video (gradation)images, character images and the like can easily be generated.

[0081] Moreover, because a pulse width addition function for thegeneration of the laser control signal ON in order that a desired laseremission can be obtained from input pixel data can be realized, themodulation of the quantity of laser light more accurate than any otherrelated art can be performed. Consequently, the high image quality canbe achieved.

[0082] Moreover, because all of the components of the pixel modulationapparatus can be structured by a pure CMOS process, the pixel modulationapparatus of the present invention can be realized cheap in cost.Consequently, the pixel modulation apparatus of the present invention isadvantageous to a multibeam/multi-drum type laser beam image formingapparatus, which needs a plurality of pixel modulation apparatus.

[0083] In other words, the foregoing description of embodiments has beengiven for illustrative purpose only and not to be construed as imposingany limitation in every respect.

[0084] The scope of the invention is, therefore, to be determined solelyby the following claims and not limited by the text of thespecifications and alterations made within a scope equivalent to thescope of the claims falling within the true sprit and scope of theinvention.

What is claimed is:
 1. A pixel modulation apparatus for converting pixeldata D composed of N1 bits input at a pixel period T0 to a pixel datasignal composed of one bit, comprising: a) a first data conversion unitwhich converts the pixel data D to pixel data D1 expanded to N2 bits(N2>N1) at the period T0; b) a second data conversion unit whichconverts the pixel data D1 to pixel data D2 composed of N3/m bits at aperiod T0/m; c) a third data conversion unit which inputs n data fromamong the pixel data D2 and pixel data Dd2 constituting the pixel dataD2 receding by the period TO/m to execute logical sum operations apredetermined number (equal to or less than n) of times to convert theinput n data to pixel data D3 composed of N3 bits, including additionaldata corresponding to the predetermined number; and d) a fourth dataconversion unit which converts the pixel data D3 to the pixel datasignal composed of one bit at the period T0/m.
 2. An apparatus accordingto claim 1, wherein said first data conversion unit includes a memorywhich stores data for a modulation of the pixel data D with a desiredpixel modulation method, and wherein said first data conversion unitinputs the pixel data D into address lines of said memory and outputsthe pixel data D1 from word lines of said memory.
 3. An apparatusaccording to claim 1, wherein said second data conversion unit and saidfourth data conversion unit severally include a serial data conversionunit composed of a predetermined bits, said serial data conversion unitbeing configured without any flip-flop circuit.
 4. An apparatusaccording to claim 1, said apparatus further comprising an image formingunit which forms an image by use of the pixel data signal converted bysaid fourth data conversion unit.
 5. An apparatus according to claim 4,wherein said image forming unit forms the image with anelectrophotographic process.
 6. An apparatus according to claim 4,wherein said image forming apparatus forms a color image by formingimages having different colors from on a plurality of photosensitivedrums respectively.
 7. An apparatus according to claim 6, wherein saidimage forming unit forms the images by irradiating two beams onto saidplurality of photosensitive drums.
 8. A pixel modulation method ofconverting pixel data D composed of N1 bits input at a pixel period T0,to a pixel data signal composed of one bit, comprising the steps of: a)converting the pixel data D to pixel data D1 expanded to N2 bits (N2>N1)at the period T0; b) converting the pixel data D1 to pixel data D2composed of N3/m bits at a period T0/m; c) inputting n data from amongthe pixel data D2 and pixel data Dd2 constituting the pixel data D2preceding by the period T0/m to execute logical sum operations apredetermined number (equal to or less than n) of times to convert theinput n data to pixel data D3 composed of N3 bits, including additionaldata corresponding to the predetermined number; and d) converting thepixel data D3 to the pixel data signal composed of one bit at the periodT0/m.
 9. A method according to claim 8, said method further comprisingthe step of: forming an image by use of the pixel data signal composedof one bit.
 10. A method according to claim 9, wherein said forming stepforms the image with an electrophotographic process.
 11. A methodaccording to claim 10, wherein said forming step forms a color image.